FPGA Division Operator

FPGA Division Operator

par Cyrill Florin Lippuner,
Number of replies: 0

Hello,

We have encountered a problem, where we have to integer divide an unsigned(32) by another unsigned(6). The operator exists ("/"), the VHDL file compiles successfully and the simulation in ModelSim works and outputs the correct values, while on the Board the operation fails. We were able to narrow the problem to this very operation. 

Did we forget something or is there a special behavior to take into account?

Thank you for your answer!