Concerning the design guide PDF, it says:
We need to generate 3 clocks:
- 50 MHz clock for the Nios II processor and all its peripherals.
- 100 MHz clock for the SDRAM controller.
- 100 MHz, -3758ps phase-shifted clock for the off-chip SDRAM component
However from what I can tell, in figure 9-2 and 9-3, the nios processor clock is tied to outclk_1 (the same that is connected to the SDRAM, hence the 100 MHz one) unlike its peripherals.
So far I assumed that was an error in the figure, as just above it says the nios should be at 50 MHz but I just want to make sure, can you confirm?
thank you