IRQ my_isr(void *context) how to make it work?

IRQ my_isr(void *context) how to make it work?

par Matthias René Wüst,
Number of replies: 14

Hello everyone,

How do we make an interrupt work (the function alt_ic_isr_register as described in 'Interrupt times measurement by softwareFile')? The counter decrements from a set value to 0, where the interrupt should occur. However, the counter goes on (underflow) and the my_isr function is never properly executed. As far as we understand it, the IRQ output (last line in the VHDL file) should correctly be set to '1', since we checked all the conditions in the corresponding if clause (c main function). 

Please the VHDL (for the counter) and c codes in the following links: 

https://www.codepile.net/pile/xd8xa9dl

https://www.codepile.net/pile/wkJq8lKz

In reply to Matthias René Wüst

Re: IRQ my_isr(void *context) how to make it work?

par René Beuchat,

Hello,

I think that if you try to simulate your design, ModelSim will provide an error when you will count down after 0, as iCounter is an unsigned value. For Quartus it should not be a problem at execution.

What it means "my_isr function is never properly executed." Not executed at all? or what append ?

Do you enter sometime in the ISR ? You can put a breakpoint in the ISR and test with the debugger what append.

Did you draw (by hand) the way your system should work.

What is the output on your console, what is working correctly what not.

Good luck.

RB

In reply to René Beuchat

Re: IRQ my_isr(void *context) how to make it work?

par Cédric Oliver Portmann,

Hello,

"What it means "my_isr function is never properly executed." Not executed at all? or what append ?" Do you enter sometime in the ISR ? You can put a breakpoint in the ISR and test with the debugger what append. 

-> The my_isr function is not executed at all. We put a breakpoint at several relevant locations however this specific function is never triggered. 

We then proceeded and added a "print" to read the values of the counter in the "while-loop" and of some relevant registers. They are all correct and should trigger IRQ, however it seems that this never happens. The counter is counting down as it should starting with a specified "reset value". 

All the best

CP


In reply to Cédric Oliver Portmann

Re: IRQ my_isr(void *context) how to make it work?

par Sylvain Jean-Roger Migaud,

Hello,

I currently have the same issue as you, did you manage to find a fix ? 

I was thinking that maybe it might be due to a bad wiring in the Plateform Designer interface (see attached screenshot) or maybe a bad option in the nios settings.

Regards,

Sylvain


Attachment Screenshot from 2020-04-02 13-50-22.png
In reply to Sylvain Jean-Roger Migaud

Re: IRQ my_isr(void *context) how to make it work?

par Sahand Kashani-Akhavan,

I see in your C code the following macro when you call alt_ic_isr_register:

COUNTER_0_IRQ

Can you check what its value is in the system.h file?

In reply to Sahand Kashani-Akhavan

Re: IRQ my_isr(void *context) how to make it work?

par Cédric Oliver Portmann,

Thanks for responding. Here the values related to the counter:




/*

 * COUNTER_0 configuration

 *

 */


#define ALT_MODULE_CLASS_COUNTER_0 COUNTER

#define COUNTER_0_BASE 0x81000

#define COUNTER_0_IRQ -1

#define COUNTER_0_IRQ_INTERRUPT_CONTROLLER_ID -1

#define COUNTER_0_NAME "/dev/COUNTER_0"

#define COUNTER_0_SPAN 32

#define COUNTER_0_TYPE "COUNTER"



In reply to Cédric Oliver Portmann

Re: IRQ my_isr(void *context) how to make it work?

par René Beuchat,

We can see here that the interrupt level is not correct. You have to correct it yourself in changing the IRQ level to the one you provided with QSYS.

Look for another slave how it is declared and do the same but putting your right interrupt level.

And verify your component, with component editor if it is associated correctly with clock and reset signals.

It's a problem encountered since many years. We told it during the labs.

Good luck.

RB

In reply to René Beuchat

Re: IRQ my_isr(void *context) how to make it work?

par Cédric Oliver Portmann,

Thanks, it worked.

We had to change:

#define COUNTER_0_IRQ 0

#define COUNTER_0_IRQ_INTERRUPT_CONTROLLER_ID 1

---------------------------------

what is the reason for the following "snap" value output: 

  • ffffff47 
  • ffffff87 
  • ffffff8b 
  • ffffff8a 
  • ffffff8a 
  • ffffff8a 

the output stays at ffffff8a.

We are a bit confused since we would expect the same value for all snaps. 

In reply to Cédric Oliver Portmann

Re: IRQ my_isr(void *context) how to make it work?

par René Beuchat,

Nice, it works now.

Thus you have your counter in down counting and generate an interrupt at 0.

What is the memory used? Cache? I assume yes to both. --> be precise when you describe your problem ! It will help us and you to find the answer.

The first line: ffffff47 means the maximum of clock cycle to go in your code, then better later (2x faster).

If you do not have a cache it's strange, but if you have a cache, the first time it's empty, then tit's filled with the code thus run faster. The little variations are not relevant.

Try to execute a flush instruction to empty the cache (select the right one), you will see the effect.

Best regards.

RB

In reply to René Beuchat

Re: IRQ my_isr(void *context) how to make it work?

par Sylvain Jean-Roger Migaud,

Hello,

I still have this issue (i tried changing COUNTER_0_IRQ to 0 and COUNTER_0_IRQ_INTERRUPT_CONTROLLER_ID to 1 but it doesn't work for me), could you explain how to specify an interrupt level in QSYS as i don't understand how I'm supposed to do that and i don't see where i could find those values.

Is it related to the soc_system_irq_mapper file in Quartus ?

Thanks for all your help !

Regards,

Sylvain



In reply to Sylvain Jean-Roger Migaud

Re: IRQ my_isr(void *context) how to make it work?

par Cédric Oliver Portmann,

Can you send us a screenshot of your platform designer? Your interrupt levels might have different numbers than ours.

In reply to Cédric Oliver Portmann

Re: IRQ my_isr(void *context) how to make it work?

par Sylvain Jean-Roger Migaud,

Hi,

Thanks a lot for your help, I don't really know were the interrupt levels are specified.

Here are two screenshots, i hope it's the relevant ones.



Otherwise could you explain quickly were you found this option in Plateform designer ?

Regards,

Sylvain

Attachment Screenshot from 2020-04-04 14-55-01.png
Attachment Screenshot from 2020-04-04 20-29-52.png
In reply to René Beuchat

Re: IRQ my_isr(void *context) how to make it work?

par Cédric Oliver Portmann,

We use OnChipMemory and therefor cache, if I am not mistaken?

In reply to Cédric Oliver Portmann

Re: IRQ my_isr(void *context) how to make it work?

par Cédric Oliver Portmann,

So we tested with the flush function ( alt_dcache_flush_all(); ) and it we get the following output: 

  • fffff3c 
  • ffffff3e 
  • ffffff40 
  • ffffff40 
  • ffffff43 
  • ffffff43 
  • ffffff43 

Which confirms your statement and therefor shows that we use cache. 

In reply to Cédric Oliver Portmann

Re: IRQ my_isr(void *context) how to make it work?

par Sahand Kashani-Akhavan,

Be careful that having an on-chip memory as your instruction memory and having a cache are two separate things. An on-chip memory is a memory outside the processor, whereas a cache is a memory inside the processor and is not externally-visible.

With respect to the interrupt numbers: If you connect an interrupt sender in Qsys to an interrupt receiver, Qsys generally assigns a number to this interrupt. This makes sense as receivers often have multiple interrupt sources, so the source needs to correspond to one of the "wires" in the multi-bit ipending register that the CPU receives.

The problem is Qsys sometimes doesn't see this interrupt number and generates a system.h file with a "-1" as the interrupt source number, which means that no interrupt source is connected. You therefore need to check the system.h file and correct any mismatches between what you read there and what you have designed in Qsys for the interrupt numberrs.