[LAB3] : JTAG DEBUG

[LAB3] : JTAG DEBUG

par Jonathan Magnin,
Number of replies: 2

Hi,

I post here because I did not find any lab3 forum.

In the lab3, we have to get each processor a "jtag debug module", but I do not understand exactly what that  means.

In the altera tutorial, they give each processor a "jtag uart" and export the "debug reset request" of each processor. So what does the jtag debug correspond to exactly ? is it also a jtag uart? is it the reset request export ? Or is it another IP and in this case, which one : "altera soft core JTAG IO" or "altera virtual JTAG" ?


Happy Easter,

Jonathan Magnin

In reply to Jonathan Magnin

Re: [LAB3] : JTAG DEBUG

par Sahand Kashani-Akhavan,

Hi,

The JTAG DEBUG module the statement refers to is automatically included if you keep the default settings of a Nios processor. I think it's in one of the last tabs in the configuration interface where it allows you to select between 4 different levels of a JTAG DEBUG interface.

The statement just wants you to be sure level 0 (i.e. no debug) is not selected. The default level should be fine (I believe it was level 1).