Hi,
I post here because I did not find any lab3 forum.
In the lab3, we have to get each processor a "jtag debug module", but I do not understand exactly what that means.
In the altera tutorial, they give each processor a "jtag uart" and export the "debug reset request" of each processor. So what does the jtag debug correspond to exactly ? is it also a jtag uart? is it the reset request export ? Or is it another IP and in this case, which one : "altera soft core JTAG IO" or "altera virtual JTAG" ?
Happy Easter,
Jonathan Magnin