Thanks for you answer. Indeed it was a memory problem. I removed the instruction connection from the Master bridge, but then the processors were not starting anymore. The Nios-II eclipse was not downloading the code on the two separate memories, but on the SDRAM.
A TA helped me fix the problem by modifying the BSP (cf. image). The memory targets were not selected properly (I thought they would when compiling with Quartus).
Now I can have the 2 JTAG-UART connected at the same time and receive information from the 2 CPUs.
