Hello,
in the manipulation on Multiprocessors, I expect 2 NIOSII processors, version with caches and the description on section 3.
When you use the UART, you can test it with the logic analyser with serial UART decoding.
3 PIOs in total: 1 for each NIOS, 1 for both.
In 3.4 we want to use the common PIO as a software counter by software accessible by both processors.
When we do a counter in a variable (represented here as the PIO), if we do something as Cnt++, it is NOT a primitive, as the processor has to execute :
- Read Cnt in an internal processor register
- Add 1 to the register
- Write back to the Cnt
If two processors have to do that a Mutex is mandatory to have exclusive access to this variable.
Here we want to represent the Cnt by the PIO data register and doing the same, but we need to do that "by hand" with IO_RD... and IO_WR... accesses. and Mutex to do exclusive access.
Now the Manipulation 4 needs that you modify your own parallel port with a primitive function to add a value which is provide by a write access to a specific register position (you decide how) that will take the actual register value and add the written data, You can do a hardware specialized unit to act as a counter accessible as a unique cycle primitive.
I hope its clear now.
Best.
RB