Hi,
My apologies for not answering earlier. I didn't know of the existence of this mini-forum and did not receive any notifications for new posts!
I know it's too late as you already presented your project and demo, but I thought I'd answer to give you some VHDL pointers.Indeed, there is no square root function in VHDL and you'd need to implement that yourself if you really want one. Quartus has a floating-point square root function, but it would require you to use a floating-point format for your operators. It's doable, but probably a too much for this course.
The docs for the FP unit in case you're interested:
https://www.intel.co.jp/content/dam/altera-www/global/ja_JP/pdfs/literature/ug/ug_altfp_sqrt_mf.pdf
The algorithm you described for squaring is correct and it should preserve signs. However, I'd advise against using the "integer" type directly in VHDL. This type represents a 32-bit integer similarly to the native data words on CPUs nowadays. You can constrain it's range in VHDL with something like this:
If constrained, the compiler infers a smaller size for the signal/register and saves space, but generally projects that use the integer type end up using way more ALM resources for nothing as most people never constrain them. I'd recommend you always use the types provided in the ieee.numeric_std library, specifically the "signed" and "unsigned" types that are like std_logic_vector as you have to explicitly provide the signal's width. However, adding/subtracting/multiplying signals of type "signed" or "unsigned" yields a result with the appropriate number of bits so precision is not lost and you always use enough bits as are necessary.
The only case where integers are really useful in VHDL is for simulation since this data type can rapidly be simulated on PCs as simulators directly use the corresponding machine assembly instruction to emulate it's behavior (unlike for std_logic_vector/signed/unsigned where a sequence of instructions may be necessary to correctly emulate their behavior).
