Hi everyone,
I would like additional instructions about the requirements of the implementation of the hardware counter, and more exactly what types of accesses are allowed.
This is because that, by default, the Avalon interconnect will do requests' arbitration, and since we make the requests in one shot, the hardware will always stay in a clean state.
This means that by default, our counter already has bare-minimum multi-master capabilities.
Now, if we want to avoid data races and provide "atomic" access or exclusive access, then we have to implement mutex-like functionality. I suppose this is what we should do, but I would like confirmation.
Regards