Real-time embedded systems

Embedded Systems course

You need to install VirtualBox on your PC and the extension pack:

https://www.virtualbox.org/wiki/Downloads

Select the ubuntu.vbox to have all the needed programms for the lab:

Quartus Prime 18.1, 
ModelSim Altera Started Edition 10.5b
ARM DS-5
NIOSII Command Shell
Altera Embedded Command Shell
FireFox

Standard user = vm
Password = 1234

Root user = root
Password = 1234

Design guide for programmable interfaces and unit for QuartusII, IntelPatform designer

Please fill the google-sheet for the groups and selected subjects

Where is time spent in an interrupt routine ?

correction dataBus Rd and Write have to be of the same size

Resume on VHDL structures

Methodology to design a test bench in VHDL for ModelSim (Sahand Kashani)

How interruptions are managed on the NIOSII processor

RTES lecture on 2021/03/01 - Parallel Port & Nios II Interrupts (part 1)

HAL Description for NIOS II softcore processor,

NII52010-11.0.0

Software Reference Data Book Description for NIOS II softcore processor,

n2sw_nii5v2

NII5V2-13.1

Video of this chapter of the course

µC/OS-II

The Real-Time Kernel

 Jean J. Labrosse

micrium

What is a custom instruction and how to use it.

Lab 2 exercise.

What is a custom instruction, and how can we do it.

How to profile with gprof an SBT, performance counter or timer

RTES lecture 2021/03/29 - NIOSII Custom Instruction & Profiling

Bus Avalon as slave and master, with timing diagrams

How can we design a multiprocessor system on an FPGA?

Use of SOC-FPGA with the DE1-SOC 

Description of DE1-SOC board from terasic

Cyclone V, HPS Technical Reference Manual

Qsys entry point doc. on Altera

Link to Design Guide documentation for DE1-SOC FPGA

Sahand Kashani, René Beuchat

Standard user = psoc
Password = 1234

Root user = root
Password = 1234