Hello,
in the Interrupt Analysis Lab, before the manipulation 5, it's written to measure our timings with 6 different configurations :
o Instruction cache disabled, data cache disabled, on-chip memory
o Instruction cache enabled, data cache disabled, on-chip memory
o Instruction cache enabled, data cache enabled, on-chip memory
o Instruction cache disabled, data cache disabled, sdram memory
o Instruction cache enabled, data cache disabled, sdram memory
o Instruction cache enabled, data cache enabled, sdram memory
I suppose that for the instruction and data cache we just have to change the config in Platform Designer of our processor, but I'm less confident with the memory : should I remove the on-chip memory block ? And how to replace it with a suited sdram ?
Thanks for your clarifications,
Théo
