Semaine Nom Description
URL "Embedded Systems" Course

Embedded Systems course

Dossier Directory
Directory files
Page Resource
URL RTES Virtual Machine for students who don't have Windows or Linux (VirtualBox)

You need to install VirtualBox on your PC and the extension pack:
https://www.virtualbox.org/wiki/Downloads
Select the ubuntu.vbox to have all the needed programm for the lab:
  • Quartus Prime 18.1,
  • ModelSim Altera Started Edition 10.5b
  • ARM DS-5
  • NIOSII Command Shell
  • Altera Embedded Command Shell
  • FireFox
Standard user = vm
Password = 1234

Root user = root
Password = 1234

Fichier RTES Standard Project Template (Updated 12/06/2016)
Fichier SoC-FPGA Design Guide [DE1-SoC Edition] 1.33
Fichier DE1-SoC Schematic
Fichier Virtual Machine launcher shell script
Fichier Embedded IP User Guide (version 15)
URL General IP link from IntelFPGA (vers 18.1)

Design guide for programmable interfaces and unit for QuartusII, IntelPatform designer

Fichier Laboratory: Interrupt analysis

Where is time spent in an interrupt routine ?


Fichier Laboratory: Interrupt Analysis template
Fichier Laboratory: Multiprocessor
Multiprocessor system on FPGA4U Laboratory
18 février - 24 février Fichier RTES Introduction (slides)
Introduction to RTES P2016
Fichier NIOSII - Avalon Bus (slides)
Avalon Bus transferts slave/master
Fichier Parallel port Implementation on Avalon Bus (slides)
Example of a programmable parallel port design for embedded system on a FPGA
Fichier Counter Programmable interface ! Updated (v2.1 slides)
An example of a specific programmable interface on Avalon Bus, a counter

correction dataBus Rd and Write have to be of the same size

Fichier VHDL resume (slides)

Resume on VHDL structures

URL Intel FPGA documentation NIOSII design
Fichier Embedded System on FPGA, simple design example
Simple NIOSII design as example of methodology
Fichier RTES 101: THE Ultimate Starter's Setup Guide
25 février - 3 mars Fichier Interrupt on NIOSII processor (slides)

How interruptions are managed on the NIOSII processor

Fichier Methodology for NIOS II system design and Peripheral design (slides, vers.1.1c)
Fichier Using NIOSII Embedded Design Suite (EDS - SBP)
Fichier Simulation with ModelSim (vers. 0.6)
Fichier Interrupt times measurement by software
URL Exception Handling on NIOSII (Altera doc)
Document from Altera on NIOS II Exception handling for Nios II Software Build Tools (SBT).
URL Main IP and Vectored Interrupt Controller (Altera doc)
Management of interruption with a Vectored Interrupt Controller on NIOSII
URL Vectored Interrupt Controller, Usage and Applications (Altera doc)
4 mars - 10 mars URL Altera, NIOSII, HAL API Reference

HAL Description for NIOS II softcore processor,

NII52010-11.0.0

URL Altera, NIOS II Software Reference Data Book, 2011

Software Reference Data Book Description for NIOS II softcore processor,

n2sw_nii5v2

NII5V2-13.1

18 mars - 24 mars Fichier "Real Time Embedded systems - MicroC/OS-II" (slides)
A general view on Real-Time OS, specifically MicroC/OS-II
Fichier Micrium uCOSII CfgMan
Fichier ucosII vers 2.86 doc RefMan
25 mars - 31 mars Fichier Custom Instruction (slides)
Fichier Profiling (slides)
Some methodologies to profile a program
URL Custom Instruction (IntelFPGA, NIOS II), dec. 2017

What is a custom instruction, and how can we do it.

Fichier Profiling Description (Altera) AN-391, July 2011
Profiling laboratory from Altera
Fichier Embedded Peripheral IP User Guide
1 avril - 7 avril Fichier NIOS II Avalon en6 EPFL
Fichier Exercice Master Avalon LAP en
Fichier Master Accelerateur (sorry in French, but VHDL exemple)
8 avril - 14 avril Fichier Multi masters, multiprocessors (slides)
URL Multiprocessor tutorial
Tutorial from Altera on multiprocessor
URL Multiprocessor design example (Altera)
2 processors design example for Web server (to be adapted to FPGA4U)
Fichier Labo Multiprocessor
15 avril - 21 avril Fichier CycloneV - SOC FPGA (slides)

Use of SOC-FPGA with the DE1-SOC 

URL DE1-SOC User Manual V0.6 (from Terasic)

Description of DE1-SOC board from terasic

URL Cyclone V Handbook (Altera >3000p.)

Cyclone V Handbook

URL Amba AXI Bus on Cyclone V (Altera)

Amba AXI bus description

URL QSYS specifications (Altera)

Qsys entry point doc. on Altera

URL SOC-FPGA Designe Guide

Link to Design Guide documentation for DE1-SOC FPGA

Sahand Kashani, René Beuchat

29 avril - 5 mai Fichier Mini-Project (slides)
Fichier Memories (slides)
Some memories specification
6 mai - 12 mai URL PrSoC Virtual Machine for students who don't have Windows or Linux (VirtualBox)

Standard user = psoc
Password = 1234

Root user = root
Password = 1234