Design of a specific Programmable Interface for FPGA
Completion requirements
Opened: Friday, 12 October 2018, 12:00 PM
Due: Sunday, 11 November 2018, 11:55 PM
Laboratory 2
You have to design and implement in VHDL a specific Programmable Interface on an FPGA. It has to be accessible by a Nios II processor. A small C program will test the design.
You have to design and implement in VHDL a specific Programmable Interface on an FPGA. It has to be accessible by a Nios II processor. A small C program will test the design.
- Please submit your report in PDF format
with the following naming convention so we can easily know who's
assignment it is without having to open up the document each time:
<student_1_name>_<student_2_name>_lab2.2CustomSlavePI.pdf
For example, if "René Beuchat" and "Sahand Kashani" submitted the assignment, we would use the following file name: "ReneBeuchat_SahandKashani_lab2.2CustomSlavePI.pdf". - Also submit a ZIP file containing your project designs. Please do not submit all temporary files generated by Quartus which inflate your submission's file size. Your submissions should be < 1 MB if you only add VHDL & C sources (*.vhd, *.c, *.h), the Quartus project base (*.qpf, *.qsf) files, and the Qsys base (*.qsys) files.
- ONLY 1 REPORT per group.