Design of master unit interface for FPGA
Completion requirements
Opened: Friday, 2 November 2018, 12:10 PM
Due: Sunday, 25 November 2018, 12:30 AM
Laboratory 3
In this group of laboratories, you will have to design a master module. It will be either an LCD display controller or a camera controller associated with a Nios II processor. Two groups have merge their designs and use both modules to a capture a picture from a camera and display it on the LCD module.
In this group of laboratories, you will have to design a master module. It will be either an LCD display controller or a camera controller associated with a Nios II processor. Two groups have merge their designs and use both modules to a capture a picture from a camera and display it on the LCD module.
- Please submit your report in PDF format
with the following naming convention so we can easily know who's
assignment it is without having to open up the document each time:
<student_1_name>_<student_2_name>_lab3.0MasterUnitInterface.pdf
For example, if "René Beuchat" and "Sahand Kashani" submitted the assignment, we would use the following file name: "ReneBeuchat_SahandKashani_lab3.0MasterUnitInterface.pdf". - Also submit a ZIP file containing your project designs. Please do not submit all temporary files generated by Quartus which inflate your submission's file size. Your submissions should be < 1 MB if you only add VHDL & C sources (*.vhd, *.c, *.h), the Quartus project base (*.qpf, *.qsf) files, and the Qsys base (*.qsys) files.