Design of an Embedded System, Mini-Project.
Completion requirements
Opened: Sunday, 25 November 2018, 12:00 PM
Due: Friday, 4 January 2019, 11:55 PM
Laboratory 4
In this group of laboratories, you will have to design a system in the FPGA of CycloneV-SoC. It could be a system able to communicate with a ARM-A9 processor.
In this group of laboratories, you will have to design a system in the FPGA of CycloneV-SoC. It could be a system able to communicate with a ARM-A9 processor.
- Please submit your report in PDF format
with the following naming convention so we can easily know who's
assignment it is without having to open up the document each time (select accordingly depending on if you designed the LT24 controller, or the TRDB-D5M controller):
<student_1_name>_<student_2_name>_lab3.1MiniProjectLT24Interface.pdf
<student_1_name>_<student_2_name>_lab3.1MiniProjectTRDBD5MInterface.pdf
For example, if "René Beuchat" and "Sahand Kashani" submitted the assignment for the TRDB-D5M controller, we would use the following file name: "ReneBeuchat_SahandKashani_lab3.1MiniProjectTRDBD5MInterface.pdf". - Also submit a ZIP file containing your project designs. Please do not submit all temporary files generated by Quartus which inflate your submission's file size. Your submissions should be < 1 MB if you only add VHDL & C sources (*.vhd, *.c, *.h), the Quartus project base (*.qpf, *.qsf) files, and the Qsys base (*.qsys) files.