Real-time embedded systems
Semaine | Nom | Description |
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"Embedded Systems" Course | Embedded Systems course |
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Directory | Directory files |
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Resource | ||
RTES Virtual Machine for students who don't have Windows or Linux (VirtualBox) | You need to install VirtualBox on your PC and the extension pack: https://www.virtualbox.org/wiki/Downloads Select the ubuntu.vbox to have all the needed programms for the lab:
Standard user = vm |
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RTES Standard Project Template (Updated 12/06/2016) | ||
SoC-FPGA Design Guide [DE1-SoC Edition] 1.33 | ||
DE1-SoC Schematic | ||
Virtual Machine launcher shell script | ||
Embedded IP User Guide (version 15) | ||
General IP link from IntelFPGA (vers 18.1) | Design guide for programmable interfaces and unit for QuartusII, IntelPatform designer |
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Laboratory: Interrupt analysis | Where is time spent in an interrupt routine ? |
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Laboratory: Interrupt Analysis template | ||
Laboratory: Multiprocessor | Multiprocessor system on FPGA4U Laboratory |
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17 février - 23 février | RTES Introduction (slides) | Introduction to RTES P2016 |
NIOSII - Avalon Bus (slides) | Avalon Bus transferts slave/master |
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Parallel port Implementation on Avalon Bus (slides) | Example of a programmable parallel port design for embedded system on a FPGA |
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Counter Programmable interface ! Updated (v2.1 slides) | An example of a specific programmable interface on Avalon Bus, a counter correction dataBus Rd and Write have to be of the same size |
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VHDL resume (slides) | Resume on VHDL structures |
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Intel FPGA documentation NIOSII design | ||
Embedded System on FPGA, simple design example | Simple NIOSII design as example of methodology |
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RTES 101: THE Ultimate Starter's Setup Guide | ||
24 février - 1 mars | Interrupt on NIOSII processor (slides) | How interruptions are managed on the NIOSII processor |
Methodology for NIOS II system design and Peripheral design (slides, vers.1.1c) | ||
Using NIOSII Embedded Design Suite (EDS - SBP) | ||
Simulation with ModelSim (vers. 0.6) | ||
Interrupt times measurement by software | ||
Exception Handling on NIOSII (Altera doc) | Document from Altera on NIOS II Exception handling for Nios II Software Build Tools (SBT). |
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Main IP and Vectored Interrupt Controller (Altera doc) | Management of interruption with a Vectored Interrupt Controller on NIOSII |
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Vectored Interrupt Controller, Usage and Applications (Altera doc) | ||
2 mars - 8 mars | Altera, NIOSII, HAL API Reference | HAL Description for NIOS II softcore processor, NII52010-11.0.0 |
Altera, NIOS II Software Reference Data Book, 2011 | Software Reference Data Book Description for NIOS II softcore processor, n2sw_nii5v2 NII5V2-13.1 |
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16 mars - 22 mars | "Real Time Embedded systems - MicroC/OS-II" (slides) | A general view on Real-Time OS, specifically MicroC/OS-II |
Micrium uCOSII CfgMan | ||
ucosII vers 2.86 doc RefMan | ||
Course on uC/OSII RTES | Video of this chapter of the course |
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23 mars - 29 mars | Custom Instruction (slides) + Lab2 | What is a custom instruction and how to use it. Lab 2 exercise. |
Profiling (slides) | Some methodologies to profile a program |
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Custom Instruction (IntelFPGA, NIOS II), dec. 2017 | What is a custom instruction, and how can we do it. |
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Profiling (IntelFPGA, NIOS II), dec. 2017 | How to profile with gprof an SBT, performance counter or timer |
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Profiling Description (Altera) AN-391, July 2011 | Profiling laboratory from Altera |
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Embedded Peripheral IP User Guide | ||
30 mars - 5 avril | NIOS II Avalon en6 EPFL | Bus Avalon as slave and master, with timing diagrams |
Exercice Master Avalon LAP en | ||
Master Accelerateur (sorry in French, but VHDL exemple) | ||
6 avril - 12 avril | Multi masters, multiprocessors (slides) | How can we design a multiprocessor system on an FPGA? |
Multiprocessor tutorial | Tutorial from Altera on multiprocessor |
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Multiprocessor design example (Altera) | 2 processors design example for Web server (to be adapted to FPGA4U) |
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Labo Multiprocessor | ||
20 avril - 26 avril | CycloneV - SOC FPGA (slides) | Use of SOC-FPGA with the DE1-SOC |
DE1-SOC User Manual V0.6 (from Terasic) | Description of DE1-SOC board from terasic |
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Cyclone V Handbook (Altera >3000p.) | Cyclone V Handbook |
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Amba AXI Bus on Cyclone V (Altera) | Amba AXI bus description |
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QSYS specifications (Altera) | Qsys entry point doc. on Altera |
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SOC-FPGA Designe Guide | Link to Design Guide documentation for DE1-SOC FPGA Sahand Kashani, René Beuchat |
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27 avril - 3 mai | Mini-Project (slides) | |
Memories (slides) | Some memories specification |
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4 mai - 10 mai | PrSoC Virtual Machine for students who don't have Windows or Linux (VirtualBox) | Standard user = psoc |
11 mai - 17 mai | i2c_sample_design |