Written report

Written report

by Daniel-Florin Dosaru -
Number of replies: 1

Dear CS-476 team,


I would like to know what should we include in the written pdf report for the first Lab:

"Provide a report with the components you created/modified in VHDL (PIO and Timer). " -> Do you want us to add the block diagram of the Counter Design and the parallel port ?

"Provide a general schematic of your design from the Buttons to the output port and external connector. " ->  Can you give us a very simple example or can you elaborate on this? 

"Provide a table with the measured times obtained by your timer and by the logic analyzer. " -> Are the results from the logic analyzer mandatory? In the today's lecture it was mentioned that this lab can be solved without the logic analyzer.


Thank you,

Daniel


In reply to Daniel-Florin Dosaru

Re: Written report

by René Beuchat -

Dear students,

For the first report, we expect to see what you learned, what you have done. 

What is in our document is what we provide and it is not necessary to repeat it.

Please use Bloc diagrams to show your design and timing diagrams to help to discuss your result.


  • We want an introduction to show what are the topics you tested.
  • In the main part: what are the programmable interface you developed and what are the modification you have done: as register map then in the VHDL code.
    What are your results with the tools you used and if more than one the differences.
    If you do not have a logic analyser to do the work, you can use another way, as the internal signal tap logic analyser of Quartus II.
  • Resume your work and discuss a minimum your results.
  • Do not forget to provide a conclusion with the tolls you used and if it is working or not.
  • Put in annex the source code of your work.

I hope it's more clear now.

Best regards and see you next week.

R.Beuchat