Dear CS-476 team,
I would like to know what should we include in the written pdf report for the first Lab:
"Provide a report with the components you created/modified in VHDL (PIO and Timer). " -> Do you want us to add the block diagram of the Counter Design and the parallel port ?
"Provide a general schematic of your design from the Buttons to the output port and external connector. " -> Can you give us a very simple example or can you elaborate on this?
"Provide a table with the measured times obtained by your timer and by the logic analyzer. " -> Are the results from the logic analyzer mandatory? In the today's lecture it was mentioned that this lab can be solved without the logic analyzer.
Thank you,
Daniel