Dear students,
For the first report, we expect to see what you learned, what you have done.
What is in our document is what we provide and it is not necessary to repeat it.
Please use Bloc diagrams to show your design and timing diagrams to help to discuss your result.
- We want an introduction to show what are the topics you tested.
- In the main part: what are the programmable interface you developed and what are the modification you have done: as register map then in the VHDL code.
What are your results with the tools you used and if more than one the differences.
If you do not have a logic analyser to do the work, you can use another way, as the internal signal tap logic analyser of Quartus II. - Resume your work and discuss a minimum your results.
- Do not forget to provide a conclusion with the tolls you used and if it is working or not.
- Put in annex the source code of your work.
I hope it's more clear now.
Best regards and see you next week.
R.Beuchat
