Dear students,
many requested to have a delay for Lab1 report. Last date is 14th of April.
An important document to be able to do your QSYS design is SoC-FPGA Design Guide DE1-SoC Edition (on moodle).
Please look on it and mainly:
Chapter 8 USING THE CYCLONE V – GENERAL INFORMATION
...
The DE1-SoC has a lot of pins, which makes it tedious to start an FPGA design. It is recommended to use the
ENTITY in [3] for your TOP-LEVEL VHDL FILE, as it contains all the board’s FPGA and HPS pins.
After having defined a top-level module, it is necessary to map your design’s pins to the ones available on the
DE1-SoC. The TCL SCRIPT in [4] can be executed in Quartus Prime to specify the board’s device ID and all its
PIN ASSIGNMENTS. In order to execute the TCL script, place it in your quartus working directory, then run it
through the “Tools > Tcl Scripts…” menu item in Quartus Prime.
...
DO NOT JUMP those requirements, the design will not work otherwise.
Chapter 9 USING THE CYCLONE V – HARDWARE
9.1 GENERAL QUARTUS PRIME SETUP
9.2 SYSTEM DESIGN WITH QSYS – NIOS II
5. Add an “Altera PLL” to the system. !!!!!!!!!!!!!!!!!!!!!!!!!! Very important (as the rest too, but too many groups jump this step !!!!!!!!)
100 MHz, -3758 ps phase-shifted clock for the off-chip SDRAM component
In Qsys’ “System Contents” tab:
Export “pll_0.outclk2” under the name “pll_0_sdram”, as shown in Figure 9-1. This clock
will be used for the off-chip SDRAM component.
6. Add a softcore SDRAM... and all the specified parameters !!!!!!!!!!!!!!!!!!!!!!!!!
-- >> Look on the qsys picture for pll export !!!!! AND DO THE SAME
Add your own programmable interface
By sure to connect the reset and vectors on the memory you want to test in the NIOS description.
That's all for now on the qsys side.
----------------------------------------------------------------------------------------------------------
On QuartusII:
Be sure to have the top level in the hierarchy specified as the file with all the pin definitions, and that you comment all unnecessary pins.
Edit the top level file and you should add your component provided by qsys. Connect to valid pin names your external connections. If you use some pins as bidirectionnal in the GPIO, change the connected pin type to inout in the entity.
Then you can compile and download.
------------------------------------------------------------------------------------------------------------
Start the Nios IDE and try the simple test "Hello World" to see if the connection and design is correct.
Good luck
RB & assistants
