Register write/read problem

Register write/read problem

par Jakub Lukasz Wieczorek,
Number of replies: 1

I still have a problem with access to the internal register in FPGA design using Address field and IOWR*DIRECT/IORD*DIRECT macros. Regardless what arguments I use it behaves very weird.  Sorry for the screens, but I wanted to keep the syntax color.


So somehow operation on one register affects the other, lets say second IOWR in the line 38 sets RegLgt to A, but apart from RegLgt also RegAddStart is changed. Below vhdl internal signals and read/write processes.


I will be grateful for help.

In reply to Jakub Lukasz Wieczorek

Re: Register write/read problem

par René Beuchat,

in your write process it miss the

if rising_edge(clk) then ...

thus, no registration of your data.

and for the read, no clk used, thus the sensitivity list is wrong.

Best.

RB