DMA accelerator

DMA accelerator

by Leonardo Mussa -
Number of replies: 3

Hello, 

I'm having some trouble with the DMA accelerator an I can't figure out why.


It works just fine but only when I set a debug breakpoint on any of the following instructions (which set up and start the circuit):


If I run the code normally, the circuit doesn't write anything in the memory. Even if I run the code in debug mode but without a breakpoint on these instructions, nothing happens. 


I really have no idea why this is happening, maybe there is some issues with the arbitration of the bus? 

Or maybe I didn't design well my circuit...  right now it does the following

         - read 32 bits 

         -  process them

         - write the result in memory (at a different location)

         - loop for every piece of data

Maybe I should have an internal buffer or a FIFO? Is it ok to read a piece of data at the time and write it immediately after?


Here is my State Machine:





And here is my VHDL code:



Thanks a lot for your help!



In reply to Leonardo Mussa

Re: DMA accelerator

by Leonardo Mussa -

I solved my issue!!! 


In case you have a similar problem here is how I solved it:

I have a cache memory on my system and this is why I was having troubles.

I wanted to write some values in the memory  to test my accelerator but the processor was writing on the cache instead than in the memory! So my accelerator was reading junk memory (zeros everywhere) and that's why it looked like it wasn't working.

To force the processor to bypass the cache and write in the memory, just use the IO_WR*DIRECT(...) macros and it will work just fine!


I hope this will help someone :)

In reply to Leonardo Mussa

Re: DMA accelerator

by René Beuchat -

Hello,

it's nice that it works.

Did you simulate your master unit?

I think you did not remove the write signal as early as necessary. In WaitForWrite, desactivate master_Write when the WaitReqest is desactivated in all cases.

For the cache, you can send the FlushD command before starting your accelerator.

Or (but not recommended any more, adding 2^31 to the address used by the processor, the cache will be bypassed.

Good night.

RB 

In reply to René Beuchat

Re: DMA accelerator

by Leonardo Mussa -

Hello and thanks for your answer.

Yes I simulated it and it seemed to work but thanks for pointing out the issue with the Write signal. I will also try to use the FlushD command.

Best

Leonardo Mussa