Accelerator Master Interface Connection

Accelerator Master Interface Connection

by Matthias René Wüst -
Number of replies: 3

Hello everybody

Concerning the accelerator DMA access: We are having trouble in C-code to print meaningful values. We tried multiple approaches with and without the IOWR_DIRECT macros. Either it doesnt change the values at all or the debugger gets stuck when we try to start the accelerator process, which leads us to beleiving that our Platform Designer configuration might be wrong. Are our accelerator signal connections correct? In addition I provide you the VHDL register configuration and a excerpt of the code in C (which doesnt work right now but might give you a better insight in what we are trying to do). 

Thank you



In reply to Matthias René Wüst

Re: Accelerator Master Interface Connection

by Sahand Kashani-Akhavan -

Hi,

I don't know why the debugger is hanging, but I suspect you are overwriting your CPU's memory incorrectly somewhere. Can you read back the registers of your accelerator and see if they have consistent values before starting the DMA? If that doesn't yield any results, then I'd insert a signaltap probe on the line and check what addresses are being read/written by your accelerator.

Be careful in your C code as you are reading back the results on line 107 without first checking that the accelerator has finished it's work. You need to poll the Finish bit in your design from C to ensure the accelerator is done before reading back any values. Also be sure you read result[0] with IORD_32DIRECT as right now you are just indexing it directly.

In reply to Sahand Kashani-Akhavan

Re: Accelerator Master Interface Connection

by René Beuchat -

It would be more probabilistic that you master dma unit is not working correctly. We don not have the source of this part.

Can you:

  1. download you design on the board? It seems yes
  2. can you start in debug mode ?
  3. if yes, when you are doing step by step, when it stops to work? If it's when you start your dma, something should be wrong with your addresses generation and/or Waitrequest management
  4. Follow the Sahand recommendation with the signal tap logic analyzer to be implemented in the design.

Good luck

RB


In reply to Sahand Kashani-Akhavan

Re: Accelerator Master Interface Connection

by Matthias René Wüst -

Thank you for your help! It was a conflicting call as you said, mixed with some confusion about the array allocation. We noticed that indeed all assignments and calls on variables accessed by the accelerator must use the DIRECT macro.