Hi,
We are a bit lost about how to set the IDE part for the two cores. Do we need a project to each core? And if so do we need two BSP projects too?
And for the memory allocation part, although we made two on-chip memory blocks on Qsys and adjusted the reset and exception vectors of each processor so they both get 8KB out of a 16KB on-chip memory. But when I open the properties of the BSP in the IDE I can only see one logical on-chip memory and the location of it on the physical address is different from the one on Qsys. The addresses of all the components there are starting after the SDRAM for some reason, so I also don't know how to create a shared memory section on the SDRAM as it's memory is non-existent in that memory range.
I can provide whatever pictures and data you need, I was just not sure what would be useful.
Thanks in advance,
Alon