[Lab 3] Memory allocation

[Lab 3] Memory allocation

by Alon Tchelet -
Number of replies: 5

Hi, 

We are a bit lost about how to set the IDE part for the two cores. Do we need a project to each core? And if so do we need two BSP projects too? 

And for the memory allocation part, although we made two on-chip memory blocks on Qsys and adjusted the reset and exception vectors of each processor so they both get 8KB out of a 16KB on-chip memory. But when I open the properties of the BSP in the IDE I can only see one logical on-chip memory and the location of it on the physical address is different from the one on Qsys. The addresses of all the components there are starting after the SDRAM for some reason, so I also don't know how to create a shared memory section on the SDRAM as it's memory is non-existent in that memory range.

I can provide whatever pictures and data you need, I was just not sure what would be useful.


Thanks in advance,

Alon

In reply to Alon Tchelet

Re: [Lab 3] Memory allocation

by Sahand Kashani-Akhavan -

Hi,

I'm a bit confused because you say you have two on-chip memory blocks in Qsys, but then you say that each processor gets 8KB out of a 16 KB on-chip memory, so they are sharing the on-chip memory?

Each CPU have a dedicated on-chip memory for code (reset and exception vector + linker script adaptation in the BSP project to ensure the .text, .data, ... regions are all in that on-chip memory). Be sure that only one CPU is connected to each on-chip memory. If this is the case, the memories will have different names such as "onchip_memory_0" and "onchip_memory_1". You should then be able to differentiate between them in the BSP project as their name will be used.

In addition to the dedicated on-chip memories, you need to add a single sdram controller to which both CPUs are connected. This is where shared data will be manually placed through calls to IO(WR|WR)_32DIRECT, or by declaring a pointer to the address in the SDRAM you want to read/write to.

Note that by default the BSP editor will always use the largest memory connected to the instruction master port of the CPU for most code/data. This corresponds to the SDRAM in your system, but if you want this code/data to be in the on-chip memory, then you need to edit the "Linker Script" tab in the BSP editor to mark these regions in the on-chip memory boundaries.

In reply to Sahand Kashani-Akhavan

Re: [Lab 3] Memory allocation

by Alon Tchelet -

Hi,

So I have two onchip memory blocks, but the physical addresses Qsys allocate them both is the same. It's like Qsys generates only on onchip memory block and the allocation is up to the designer. When saying I allocated 8KB to each is because I set the reset and exception vectors of the second cpu to start in an 8KB offset from the beginning of the onchip memory start address.

I only see a single onchip memory on the BSP. So I think my problem starts in Qsys. Would it be advisable to manually split the onchip memories by changing they base and end addresses in Qsys?

Last point, if we planned using the SDRAM only for shared memory, would we still need to connect it to the instructions line?

In reply to Alon Tchelet

Re: [Lab 3] Memory allocation

by Sahand Kashani-Akhavan -
The addresses that Qsys shows you are those seen by the master to which the slave is connected. If both CPUs are only connected to their own on-chip memory, then it's highly-probably Qsys assigns the same physical address to them. You therefore must not assign the 2nd CPU's reset and exception vectors to an 8KB offset from the first as there is no "first CPU" using this memory.

It's normal to see a single on-chip memory in the BSP editor as you need a BSP for each CPU (CPUs are independent and use their own code/data).

Shared memory is for data, not code. So it's unnecessary to connect the shared SDRAM controller to either CPU's instruction_master port.
In reply to Sahand Kashani-Akhavan

Re: [Lab 3] Memory allocation

by Alon Tchelet -

Hi, 

We tried what you said, but onchip memories are still sharing a start address. Could we arrange a zoom call?

Best wishes,

Alon and Maxime

In reply to Alon Tchelet

Re: [Lab 3] Memory allocation

by Sahand Kashani-Akhavan -

Hi,

Are you in the lab session? We can check out your issue there.

Can you post a picture of your Qsys system as it's easier to see what's going on with a picture rather than through a description. It's normal for the on-chip memories to have the same start address if they are connected to different masters. Check the "address map" tab in Qsys and you should see multiple masters, each connected to a different set of peripherals, but some share identical addresses.