Hello,
I am currently setting up the multiprocessor system as proposed in the tutorial: https://www.altera.com/content/dam/altera-www/global/en_US/pdfs/literature/tt/%20tt_nios2_multiprocessor_tutorial.pdf
I was able to add all components that we need and it compiled well. (Basically remove philosopher_one,two,three,four,five but leave philosopher_zero) My issue comes now with the top_level file:
How can I change the top_level file to VHDL since the one in the tutorial is in Verilog and what needs to be changed?
Is there anything else necessary to change than just this top-level file if we want to adapt the code from the previous labs to the new multi processor system?
Thanks