In reading the VHDL code, we see that many of you use the bad construction in a process:
if (clk'event and clk ='1') then
...
This is very very very old way to do the way that we expect a rising edge on the clk. In general it is coming from VHDL code found on Internet :(
Thus use the function available in the ieee.std_logic_1164.all library since around than 30 years!
if rising_edge(clk) then
...
This function specify clearly what is expected!
The same with falling_edge(Clk).
RB
