Hi,
1) This seems very weird indeed. You don't have any microSD card inserted into the board by any chance? Or some switches on the board that aren't set to default values? It may be that your board is trying to boot another sequence, is misconfigured or simply defective. If this doesn't resolve, you could try switching to another board that you can grab at the LAP.
2) jtagserver should launch with Eclipse Nios II. If everything else fail, you can try to close everything, "killall jtagserver" and "killall gdbserver", and then restart Eclipse. Also, if you have ran code on the Nios II CPU and it failed to stop the debugging properly (for instance if you are unable to stop the debugging session) then the JTAG connection will become unresponsive, and you'll need to reset the power on the board (and reprogram the FPGA).
3) It really depends on your code. For a read to take 0.7 us = 700ns ~ 35 clock cycles is not necessarily surprising. It really depends on which bus accesses you perform at what point in time, for instance you also need to consider that the read / writes to your peripherals (timer, GPIO) also take some time, and caches and memory types may also affect your timings if you use load / stores from memory. I can't really say in the general case, if you want to take these in consideration you would need to do it on a per-project basis.
I understand that it may be frustrating to fight against the tools (and I cannot argue with the fact that the Quartus suite is not very developer-friendly) however in some sense we also consider this to be part of the assignment and, more generally, engineering work. The unfortunate truth is that many systems are complex, not necessarily well-designed and may also have crappy documentation; Quartus and Nios II are used in industrial projects, and it is also part of the role of engineers to learn the tools of the trade or find / create better alternatives.
I hope this helps and do not hesitate to let us know if you have questions,
Best,
The TAs Team
