Weekly outline

  • Real Time Embedded Systems, CS-476

    Type of teaching

    Ex cathedra, laboratories and a miniproject

    In Line video meeting/course:

    rene.beuchat@epfl.ch is inviting you to a scheduled Zoom meeting.

    NEW channel:


    Recorded lectures on SwitchTube:


    Final mini-project presentation

    Please fill the doodle when you will be ready do to your mini-project final presentation.


    Required prior knowledge

    Embedded Systems, Real time Programming, VHDL


    A real time system has to accept important temporal constraints. A real time embedded system must be able to react to events with a limited time.
    During this course, the measures of response time to interruptions are studied and tested in laboratories, such as for example the influence of dynamic memories, of cache memories, of option of compilation. Measurements of response time to the interruptions, tasks commutations, primitives of synchronizations are carried out on an embedded system based on a FPGA.
    Multiprocessors, accelerators, custom instructions, specialized hardware are some ways to improve the performance of a specific application. Those concepts are developed through laboratories and a mini-project.


    The course includes the study of models of management of an embedded system by polling, interruptions and using a real time kernel and these primitives of tasks management and synchronizations.
    Specialized programmable interfaces are carried out in VHDL to help with these measurements. A real time kernel is studied and used at the time of the laboratories. A system of acquisition is carried out and the gathered data transmitted by an embedded Web server. To ensure the real time acquisition and reading by the Web server, a multiprocessor system is developed and carried out on FPGA. An Accelerator makes it possible to facilitate the optimization of functions by hardware on FPGA. Cross development tools are used.

    Each topic is treated by a theoretical course and an associated laboratory. The laboratories are realized on a FPGA board especially developed for teaching. A real time operating system is studied and used with the laboratories.

    Students work

    The students will have to implement a full embedded system based on a FPGA and softcore NIOSII processors and/or an hardcore ARM-A9 multi-processors. Embedded operating system, specialized interfaces and specific architectures are the basics tools of the course.
    You will have to develop a system as a Web server with specialized functions. A final presentation and demonstration will be part of the evaluation. Regular work reports complete the evaluation.


    Teaching notes and suggested reading material
    Specialized datasheet and norms

    Systèmes embarqués temps réel, CS-476

    Forme d'enseignement

    Ex-cathedra, laboratoires dirigés et mini-projet


    Systèmes embarqués, programmation temps réel, VHDL


    Un système temps réel doit répondre à des contraintes temporelles importantes. Un système embarqué temps réel doit être capable de répondre à des évènements avec un temps borné.
    Lors de ce cours, les éléments déterminants de temps de réponses à des interruptions sont étudiés et testés en laboratoires, comme par exemple l'influence d'une mémoire dynamique, d'une mémoire cache, d'option de compilation. Des mesures de temps de réponses aux interruptions, de commutations de tâches, de primitives de synchronisations sont réalisées sur un système embarqué basé sur une FPGA.


    Le cours comprend l'étude de modèles de gestion d'un système embarqué par scrutation, par interruptions et à l'aide d'un noyau temps réel et de ses primitives de gestion de tâches et de synchronisations.
    Des modules interfaces sont réalisés en VHDL pour aider à ces mesures. Un noyau temps réel est étudié et utilisé lors des laboratoires. Un système d'acquisition est réalisé et les données acquises transmises par un serveur web embarqué.
    Pour assurer le lien entre acquisition temps réel et lecture par le serveur web, un système multiprocesseur est développé et réalisé sur FPGA. 
    Des outils de développement croisés sont utilisés.

    Chaque thème est traité par un cours théorique et un laboratoire associé. L'ensemble des laboratoires est effectué sur des cartes spécialement développées pour ce cours. Un système d'exploitation temps réel est étudié et utilisé avec les laboratoires.
  • 22 February - 28 February

    By ZOOM and in INF3

    distribution of DE1-soc board

    (1) 3h lecture


      Review from Embedded System course/VHDL

      • VHDL review
      • NIOS II based system review
      • Avalon bus system
      • Design of a specific programmable interface

      1h exercice

      • Simple Parallel Port Design or Timer, Quartus Tools overview
    • 1 March - 7 March

    • 8 March - 14 March

      (3) 1h lecture / 3h laboratory

      This Monday is a 1 hour only lecture and 3h for laboratory,

      Come with your question about design of the timer/parallel port or VHDL.
      We will finish in the class room the design of the timer module together if necessary.

      This course is optional for the students who have followed the course "Embedded Systems", and mandatory if you are in trouble with VHDL and the design of programmable interface.

      End of Timing Analysis

    • 15 March - 21 March


      4h laboratory  --> INF 3

      End of Timing measurement, Interruptions

    • 22 March - 28 March

      (5)  2h lecture / 2h laboratory

      Real-time operating system

      • uC/OS-II principle
      • primitives
      • semaphore, event, message, tasks, ...

      • Laboratory on OS performance measurement

      Ref, tutorial on MicroC/OSII with NIOS SBP software:


    • 29 March - 4 April

      (6) 2h lecture / 2h laboratory

      Program profiling

      • Hardware profiling
      • Software profiling
      • Specific counter profiling
      • Custom Instruction
      • Accelerator on FPGA
      • DMA unit (masters)

      • Laboratory on profiling, custom instruction ans hardware accelerator

      Report on profiling, custom instruction and hardware accelerator --> see assignments



    • 5 April - 11 April

      Vacances de Pâques
    • 12 April - 18 April

      (7) 4h laboratory, with short presentation 

      Mandatory for students that didn't follow Embedded Systems !!

      • Laboratory on Custom instruction and accelerator (continue)

      Report date --> see assignments

    • 19 April - 25 April

      (8) 2h lecture / 2h laboratory

      Multi-masters system on FPGA

      • DMA unit
      • Accelerators
      • Multiprocessors
      • Communication between multiprocessors, some models
      • memories

      Ref: http://www.altera.com/literature/tt/tt_nios2_multiprocessor_tutorial.pdf

    • 26 April - 2 May

    • 3 May - 9 May

      (10) 1h course / 3h laboratory

      Answer to question for LAB 2 and 3

      • Laboratory on Multiprocessor system with DE1-SOC system

      Mini projects definition

      • Proposition of mini-projects
      • Group of 2 students (usually)
      • Start of system architecture

      • Laboratory, start of mini project

      Hardcore multi-processor & FPGA

      • Example of Cyclone V - SOC

      Mini-Project selection

      During the mini-project you have to create and develop a multimaster system.

      • One of the master is an ARM (baremetal coding or Linux)  or NIOSII processor with a RTOS and could run as a Web server
      • Another master can be a second ARM or NIOSII processor dedicated to real-time application, and will generate data for the 1st processor. It could be a specialized unit with DMA capabilities as an accelerator

      You have to propose your choice for the project and analyze the architecture for hardware design part and software. Specifically for synchronization between the processors.


      A report is due by group and a final oral presentation and a demonstration. 

      Some subjects

      • Analog data acquisition through an SPI interface (4 channels)
      • Audio player
      • Camera interface for a Web server
      • Linux web server for FPGA services
      • Camera on a Web server
      • Pictures viewer on the FPGA from a Web browser
      • A SD card Reader/Writer, data on a Web server
      • Audio In, processing, Audio Out
      • Data logger of A/D, i2c, SPI interfaces
      • Data filtering from a camera interface or image (i.e. contour extraction, math. morphology, filter, rotation, zooming, etc..)
      • Thermal Camera IR, could be stereoscopic
      • LCD TFT24, VGA as display
      • … your own idea

      In all case, do a profiling of your project and analyze the performance of your system.

      Compare with a software only solution.

    • 10 May - 16 May

      (11) 4h laboratory

      Time for laboratory, Mini project start

    • 17 May - 23 May

      (12) 4h laboratory


      Deadline for the report --> 
      Final report the 10th of June.

    • 24 May - 30 May

      Pentecôte, no course !
    • 31 May - 6 June

      (13) Mini project work

    • 7 June - 13 June

      (15) Normal final oral presentation and demo for all the groups.

      Provide your slides before your presentation. 

      15min/group max.

      - Resume of your mini-project, 5 slides with :
      • what is the goal of the mini-project
      • global architecture
      • specific topics
      • results
      • conclusion
      - Demo
      - Question

      In your report, please prepare a one page resume of your project with some general block diagrams of your system architecture.

      Normal delay 7th of June

      But we can have the presentation the next week, a doodle will be activate for your choice

    • 14 June - 20 June

      (16) Mini-project work presentation

      Really the last date for Mini-project presentation

      Please fill the calendar with all your available dates:

      15'/group for the presentation and demo 

      • goal
      • general architecture (bloc diagram, algorithms)
      • your design
      • results
      • conclusion
      • demo

      10' for questions

      5' for group change