Week Name Description
URL "Embedded Systems" Course

Embedded Systems course

Folder Directory
Directory files
Page Resource
URL RTES Virtual Machine for students who don't have Windows or Linux (VirtualBox)

You need to install VirtualBox on your PC and the extension pack:
Select the ubuntu.vbox to have all the needed programms for the lab:
  • Quartus Prime 18.1,
  • ModelSim Altera Started Edition 10.5b
  • ARM DS-5
  • NIOSII Command Shell
  • Altera Embedded Command Shell
  • FireFox
Standard user = vm
Password = 1234

Root user = root
Password = 1234

File RTES Standard Project Template (Updated 12/06/2016)
File SoC-FPGA Design Guide [DE1-SoC Edition] 1.33
File DE1-SoC Schematic
File Virtual Machine launcher shell script
File Embedded IP User Guide (version 15)
URL General IP link from IntelFPGA (vers 18.1)

Design guide for programmable interfaces and unit for QuartusII, IntelPatform designer

URL Google sheet for mini-project choice and groups

Please fill the google-sheet for the groups and selected subjects

File Laboratory: Interrupt analysis

Where is time spent in an interrupt routine ?

File Laboratory: Interrupt Analysis template
File Laboratory: Multiprocessor
Multiprocessor system on FPGA4U Laboratory
22 February - 28 February File RTES Introduction (slides)
Introduction to RTES P2016
File NIOSII - Avalon Bus (slides)
Avalon Bus transferts slave/master
File Parallel port Implementation on Avalon Bus (slides)
Example of a programmable parallel port design for embedded system on a FPGA
File Counter Programmable interface ! Updated (v2.1 slides)
An example of a specific programmable interface on Avalon Bus, a counter

correction dataBus Rd and Write have to be of the same size

File VHDL resume (slides)

Resume on VHDL structures

URL Intel FPGA documentation NIOSII design
File Embedded System on FPGA, simple design example
Simple NIOSII design as example of methodology
File RTES 101: THE Ultimate Starter's Setup Guide
URL (Video) 2021-02-22 Introduction

RTES lecture on 2021/02/22 (first hour) - Introduction

URL (Video) 2021-02-22 NIOSII - Avalon Bus

RTES lecture on 2021/02/22 (part 2) - Avalon Bus

File TestBench for Simulation

Methodology to design a test bench in VHDL for ModelSim (Sahand Kashani)

1 March - 7 March File Interrupt on NIOSII processor (slides)

How interruptions are managed on the NIOSII processor

File Methodology for NIOS II system design and Peripheral design (slides, vers.1.1c)
File Using NIOSII Embedded Design Suite (EDS - SBP)
File Simulation with ModelSim (vers. 0.6)
File Interrupt times measurement by software
URL Exception Handling on NIOSII (Altera doc)
Document from Altera on NIOS II Exception handling for Nios II Software Build Tools (SBT).
URL Main IP and Vectored Interrupt Controller (Altera doc)
Management of interruption with a Vectored Interrupt Controller on NIOSII
URL (Video) 2021-03-01 Parallel Port & Nios II Interrupts

RTES lecture on 2021/03/01 - Parallel Port & Nios II Interrupts (part 1)

8 March - 14 March URL Altera, NIOSII, HAL API Reference

HAL Description for NIOS II softcore processor,


URL Altera, NIOS II Software Reference Data Book, 2011

Software Reference Data Book Description for NIOS II softcore processor,



URL (Video) 2021-03-08 Nios II Interrupts (part 2)

RTES lecture (1h) on 2021/03/08 - Nios II Interrupts (part 2)

22 March - 28 March File "Real Time Embedded systems - MicroC/OS-II" (slides)
A general view on Real-Time OS, specifically MicroC/OS-II
File Micrium uCOSII CfgMan
File ucosII vers 2.86 doc RefMan
File Course on uC/OSII RTES

Video of this chapter of the course



The Real-Time Kernel

 Jean J. Labrosse


URL (Video) 2021/03/22 MicroC/OS-II

RTES lecture 2021/03/22 - MicroC/OS-II

29 March - 4 April File Custom Instruction (slides) + Lab2

What is a custom instruction and how to use it.

Lab 2 exercise.

File Profiling (slides)
Some methodologies to profile a program
URL Custom Instruction (IntelFPGA, NIOS II), dec. 2017

What is a custom instruction, and how can we do it.

URL Profiling (IntelFPGA, NIOS II), dec. 2017

How to profile with gprof an SBT, performance counter or timer

File Profiling Description (Altera) AN-391, July 2011
Profiling laboratory from Altera
File Embedded Peripheral IP User Guide
URL (Video) 2021/03/29 NIOSII Custom Instruction & Profiling

RTES lecture 2021/03/29 - NIOSII Custom Instruction & Profiling

12 April - 18 April File NIOS II Avalon en6 EPFL

Bus Avalon as slave and master, with timing diagrams

File Exercice Master Avalon LAP en
File Master Accelerateur (sorry in French, but VHDL exemple)
19 April - 25 April File Multi masters, multiprocessors (slides)

How can we design a multiprocessor system on an FPGA?

URL Multiprocessor tutorial
Tutorial from Altera on multiprocessor
URL Multiprocessor design example (Altera)
2 processors design example for Web server (to be adapted to FPGA4U)
File Labo Multiprocessor
URL (Video) 2021/04/19 Multi Masters Systems

RTES lecture 2021/04/19 - Multi Masters Systems

26 April - 2 May File CycloneV - SOC FPGA (slides)

Use of SOC-FPGA with the DE1-SOC 

URL DE1-SOC User Manual V0.6 (from Terasic)

Description of DE1-SOC board from terasic

URL Cyclone V Handbook (Altera >3000p.)

Cyclone V Handbook

URL Amba AXI Bus on Cyclone V (Altera)

Amba AXI bus description

URL QSYS specifications (Altera)

Qsys entry point doc. on Altera

URL SOC-FPGA Designe Guide

Link to Design Guide documentation for DE1-SOC FPGA

Sahand Kashani, René Beuchat

3 May - 9 May File Mini-Project (slides)
File Memories (slides)
Some memories specification
10 May - 16 May URL PrSoC Virtual Machine for students who don't have Windows or Linux (VirtualBox)

Standard user = psoc
Password = 1234

Root user = root
Password = 1234

17 May - 23 May File i2c_sample_design