Hello,
We first tried to implement everything at the same level but as we saw that it was really hard to debug, we've decided to have a hierarchy similar to the one in the tutorial. The problem is that we have some questions regarding their implementation:
1) Why do they have the mutex in each subsystem?
2) With the SDRAM memory we need to increase the bridges width. Indeed we had "Error: soc_system.cpu_1_0.outgoing_master: leds_0.s1 (0x4000000..0x400000f) is outside the master's address range (0x0..0x3ffffff)" which we guess is due to the size of the SDRAM. However when we try to round the bridges width to a power of two (32) it says that we are limited to 30 which is not a problem but scares us. Are we suppose to modify the width?
3) Do we also need two bridges: one for the sysid and one for the led?
Thanks in advance.
