Lab3.4: Hardware counter

Re: Lab3.4: Hardware counter

by René Beuchat -
Number of replies: 0

What is the problem of a variable (variable in a shared area as programmable interface or memory) accessed by 2 master units? Same kind of problem as for shared variables in a multi-tasking system: the atomic access for modification + the cache utilisation.

The idea through this laboratory question is to find a way to increment a counter without reading the value by the processor, modifying it and writing it back. As we could have interleaving between the master's accesses.

Thus the proposition is to do the incrementation by writing a value to add to the one in the unit, in our case a programmable interface. You can take your developped counter or parallel port to do that by simple added an register access in its register map with the value to add to the actual data content. If you are working in 2's complement the value to add can be positive or negative.

I hop it is clear.

Thus a simple write with the value to add can be done in an atomic way, without interleaved Read-modify-write.

If you use (with the NIOSII) the IOxx write access, the cache is not used, otherwise a flush is mandatory.