seed_t is defined in a package I made, here is the definition if needed:
subtype inner_seed_st is std_logic_vector;
type seeds_t is array (natural range<>) of std_logic_vector;
type seeds_array_t is array (natural range<>) of seeds_t;
And yes, I would like to do that as it is used only to give initial values to pseudo random generators, so only needed at the start of the system, I am affraid that the FPGA may already be a bit full with all the neurons I try to fit in to add the seeds somewhere on the board
