Hi,
I was trying to do exercises 3 and 4 of lab 1 and I would have some questions regarding the system we have to implement.
Firstly, I would ask what is the purpose of the performance counter (the one from the library) and of the parallel input/output port (also from the library). Indeed, I do not understand why we need these two IPs if we are required to design a custom counter and a custom parallel port ourselves. Also, I cannot find the two mentioned IPs in the Quartus library.
Secondly, I am not sure if I have fully understood why we need the SDRAM controller in our system.
Thank you in advance.
