Real-time embedded systems
Aperçu des semaines
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Real Time Embedded Systems, CS-476
The course will be in INF 3 all the times
Tools
- Please use version 18.1 of QuartusII and ModelSim, NIOS IDE available on intelFPGA,
- the Lite edition is enough, the standard needs a license provided during the course
- https://www.intel.ca/content/www/ca/en/products/details/fpga/development-tools/quartus-prime/resource.html
- Windows: https://cdrdv2.intel.com/v1/dl/getContent/665990/666029?filename=Quartus-lite-18.1.0.625-windows.tar
- Linux: https://cdrdv2.intel.com/v1/dl/getContent/665988/666036?filename=Quartus-lite-18.1.0.625-linux.tar
Type of teaching
Ex cathedra, laboratories and a miniproject
https://epfl.zoom.us/j/83148827928
Recorded lectures on SwitchTube, old sessions of 2021:
https://mediaspace.epfl.ch/channel/CS-476+Real-time+embedded+systems/30887
Final mini-project presentationPlease fill the doodle when you will be ready do to your mini-project final presentation.
to be added
Required prior knowledge
Embedded Systems, Real time Programming, VHDL
Objectives
A real time system has to accept important temporal constraints. A real time embedded system must be able to react to events with a limited time.
During this course, the measures of response time to interruptions are studied and tested in laboratories, such as for example the influence of dynamic memories, of cache memories, of option of compilation. Measurements of response time to the interruptions, tasks commutations, primitives of synchronizations are carried out on an embedded system based on a FPGA.
Multiprocessors, accelerators, custom instructions, specialized hardware are some ways to improve the performance of a specific application. Those concepts are developed through laboratories and a mini-project.Content
The course includes the study of models of management of an embedded system by polling, interruptions and using a real time kernel and these primitives of tasks management and synchronizations.
Specialized programmable interfaces are carried out in VHDL to help with these measurements. A real time kernel is studied and used at the time of the laboratories. A system of acquisition is carried out and the gathered data transmitted by an embedded Web server. To ensure the real time acquisition and reading by the Web server, a multiprocessor system is developed and carried out on FPGA. An Accelerator makes it possible to facilitate the optimization of functions by hardware on FPGA. Cross development tools are used.
Each topic is treated by a theoretical course and an associated laboratory. The laboratories are realized on a FPGA board especially developed for teaching. A real time operating system is studied and used with the laboratories.Students work
The students will have to implement a full embedded system based on a FPGA and softcore NIOSII processors and/or an hardcore ARM-A9 multi-processors. Embedded operating system, specialized interfaces and specific architectures are the basics tools of the course.
You will have to develop a system as a Web server with specialized functions. A final presentation and demonstration will be part of the evaluation. Regular work reports complete the evaluation.Bibliography
Teaching notes and suggested reading material
Specialized datasheet and normsSystèmes embarqués temps réel, CS-476
Forme d'enseignement
Ex-cathedra, laboratoires dirigés et mini-projet
Prérequis
Systèmes embarqués, programmation temps réel, VHDL
Objectifs
Un système temps réel doit répondre à des contraintes temporelles importantes. Un système embarqué temps réel doit être capable de répondre à des évènements avec un temps borné.
Lors de ce cours, les éléments déterminants de temps de réponses à des interruptions sont étudiés et testés en laboratoires, comme par exemple l'influence d'une mémoire dynamique, d'une mémoire cache, d'option de compilation. Des mesures de temps de réponses aux interruptions, de commutations de tâches, de primitives de synchronisations sont réalisées sur un système embarqué basé sur une FPGA.Contenu
Le cours comprend l'étude de modèles de gestion d'un système embarqué par scrutation, par interruptions et à l'aide d'un noyau temps réel et de ses primitives de gestion de tâches et de synchronisations.
Des modules interfaces sont réalisés en VHDL pour aider à ces mesures. Un noyau temps réel est étudié et utilisé lors des laboratoires. Un système d'acquisition est réalisé et les données acquises transmises par un serveur web embarqué.
Pour assurer le lien entre acquisition temps réel et lecture par le serveur web, un système multiprocesseur est développé et réalisé sur FPGA.
Des outils de développement croisés sont utilisés.
Chaque thème est traité par un cours théorique et un laboratoire associé. L'ensemble des laboratoires est effectué sur des cartes spécialement développées pour ce cours. Un système d'exploitation temps réel est étudié et utilisé avec les laboratoires.-
You need to install VirtualBox on your PC and the extension pack:
https://www.virtualbox.org/wiki/Downloads
Select the ubuntu.vbox to have all the needed programms for the lab:
- Quartus Prime 18.1,
- ModelSim Altera Started Edition 10.5b
- ARM DS-5
- NIOSII Command Shell
- Altera Embedded Command Shell
- FireFox
Standard user = vm
Password = 1234
Root user = root
Password = 1234 -
Important document provided as reference for the use of DE1-SoC board and tools.
READ IT
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All schematics from Terasic of the DE1-SoC board. To be used as reference if specific low level access is needed.
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If you use the VM, a very useful script.
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The intel-FPGA documentation on IP available with QuartusII. Could be very useful when you need to use them.
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Design guide for programmable interfaces and unit for QuartusII, IntelPatform designer, version 21.4
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Personal project, or by group of 2. You will have to make a presentation of 10' + 5' for demo and questions. And a report. For the presentation, provide few slides, to give on moodle with the report and projects files.
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Please fill the google-sheet for the groups and selected subjects
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INF3
distribution of DE1-soc board
(1) 3h lecture
Introduction
Review from Embedded System course/VHDL
- VHDL review
- NIOS II based system review
- Avalon bus system
- Design of a specific programmable interface
1h exercice
- Simple Parallel Port Design or Timer, Quartus Tools overview
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(2) 2h lecture / 2h laboratory
NIOS II architecture and interrupts
- interrupt latency/response time/recovery measurement
- programmable interfaces to help measurement
Laboratory on NIOS II interrupt, time measurement
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(3) 1h lecture / 3h laboratory
This Monday is a 1 hour only lecture and 3h for laboratory,
Lecture:
Come with your question about design of the timer/parallel port or VHDL.
We will finish in the class room the design of the timer module together if necessary.
This course is optional for the students who have followed the course "Embedded Systems", and mandatory if you are in trouble with VHDL and the design of programmable interface.
Laboratory:
End of Timing Analysis -
(4)
4h laboratory --> INF 3
End of Timing measurement, Interruptions
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(5) 2h lecture / 2h laboratory
Real-time operating system
- uC/OS-II principle
- primitives
- semaphore, event, message, tasks, ...
- Laboratory on OS performance measurement
Ref, tutorial on MicroC/OSII with NIOS SBP software: -
(6) 2h lecture / 2h laboratory
Program profiling
- Hardware profiling
- Software profiling
- Specific counter profiling
- Custom Instruction
- Accelerator on FPGA
- DMA unit (masters)
- Laboratory on profiling, custom instruction and hardware accelerator
Report on profiling, custom instruction and hardware accelerator --> see assignments
Ref:
http://www.altera.com/literature/lit-nio2.jsp-
What is a custom instruction and how to use it.
Lab 2 exercise.
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Some methodologies to profile a program
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(7) 4h laboratory, with short presentation
- Laboratory on Custom instruction and accelerator (continue)
Report date --> see assignments
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Bus Avalon as slave and master, with timing diagrams
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Vacances de Pâques
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(8) 2h lecture / 2h laboratory
Multi-masters system on FPGA
- DMA unit
- Accelerators
- Multiprocessors
- Communication between multiprocessors, some models
- memories
Ref: http://www.altera.com/literature/tt/tt_nios2_multiprocessor_tutorial.pdf
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(9) 1h course / 3h laboratory
- Laboratory on Multiprocessor system with DE1-SOC system
Some links to useful and full documentations on tools, boards and FPGA Cyclone V -
(10) 1h course / 3h laboratory
Answer to question for LAB 3
- Laboratory on Multiprocessor system with DE1-SOC system
Mini projects definition
- Proposition of mini-projects
- Group of 2 students (usually)
- Start of system architecture
- Laboratory, start of mini project
Hardcore multi-processor & FPGA
- Example of Cyclone V - SOC
Mini-Project selection
During the mini-project you have to create and develop a multimaster system.
- One of the master is an ARM (baremetal coding or Linux) or NIOSII processor with a RTOS and could run as a Web server
- Another master can be a second ARM or NIOSII processor dedicated to real-time application, and will generate data for the 1st processor. It could be a specialized unit with DMA capabilities as an accelerator
You have to propose your choice for the project and analyze the architecture for hardware design part and software. Specifically for synchronization between the processors.
Grade
A report is due by group and a final oral presentation and a demonstration.
Some subjects- Analog data acquisition through an SPI interface (4 channels)
- Audio player
- Camera interface for a Web server
- Linux web server for FPGA services
- Camera on a Web server
- Pictures viewer on the FPGA from a Web browser
- A SD card Reader/Writer, data on a Web server
- Audio In, processing, Audio Out
- Data logger of A/D, i2c, SPI interfaces
- Data filtering from a camera interface or image (i.e. contour extraction, math. morphology, filter, rotation, zooming, etc..)
- Thermal Camera IR, could be stereoscopic
- LCD TFT24, VGA as display
- … your own idea
In all case, do a profiling of your project and analyze the performance of your system.
Compare with a software only solution.
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(11) 4h laboratory
Time for laboratory, Mini project start
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Virtual Machine for Linux tools for DE0-nano-SOC / DE1-SOC boards
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Standard user = psoc
Password = 1234
Root user = root
Password = 1234
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(12) 4h laboratory
Mini-Project
Deadline for the report -->
Final report the 5th of June. -
(13) Mini project work
If ready, you can do your presentation this Monday morning:
https://doodle.com/meeting/participate/id/eng1JlEa
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Lundi de Pentecôte
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(14) Normal final oral presentation and demo for all the groups.
Doodle for presentation schedule, new for 2023!:
https://doodle.com/meeting/participate/id/eng1JlEa
Duration: 20'/group for presentation and demonstration, 10' for questions
Provide your slides before your presentation.
15min/group max. for the presentation !
- Resume of your mini-project, 5 slides with :- what is the goal of the mini-project
- global architecture
- specific topics
- results
- conclusion
- Question
Normal delay 5th of June
In your report, please prepare a one page resume of your project with some general block diagrams of your system architecture.
