Hello,
I have a weird error that did not happen with other project and I do not have any clue about how to solve it.
I have a space in my user name on Windows, that fact led me to install, store and work with quartus only from folder comming direcly from my C:\
The problem is that, for this project and new ones that I created to test, Quartus suddently decide to create temporary file in my Temp folder on windows (C:\Users\Andy P\AppData\Local\Temp). As you can guess this creates an error in compilation because of the space.
This files are related to some IP component I use in Qsys, the timer is always the first but others such as pll also create this mistake.
Here is some of my compilation messages :
Info (12250): Timer_0: Starting RTL generation for module 'test_soc_system_timer_0'
Info (12250): Timer_0: Generation command is [exec C:/intelFPGA_lite/18.1/quartus/bin64//perl/bin/perl.exe -I C:/intelFPGA_lite/18.1/quartus/bin64//perl/lib -I C:/intelfpga_lite/18.1/quartus/sopc_builder/bin/europa -I C:/intelfpga_lite/18.1/quartus/sopc_builder/bin/perl_lib -I C:/intelfpga_lite/18.1/quartus/sopc_builder/bin -I C:/intelfpga_lite/18.1/quartus/../ip/altera/sopc_builder_ip/common -I C:/intelfpga_lite/18.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_timer -- C:/intelfpga_lite/18.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_timer/generate_rtl.pl --name=test_soc_system_timer_0 {--dir=C:/Users/Andy P/AppData/Local/Temp/alt9488_7887259226826515847.dir/0003_timer_0_gen/} --quartus_dir=C:/intelfpga_lite/18.1/quartus --verilog {--config=C:/Users/Andy P/AppData/Local/Temp/alt9488_7887259226826515847.dir/0003_timer_0_gen//test_soc_system_timer_0_component_configuration.pl} --do_build_sim=0 ]
Info (12250): Timer_0:
Info (12250): Timer_0: ERROR:
Info (12250): Timer_0: Can't find config file 'C:/Users/Andy'
Error (12252): Timer_0: Failed to generate module test_soc_system_timer_0
I hope that there is a parameter somewhere that I can change to solve this issue but I cannot find it.
Thank you in advance
Andy Piantoni
