We were thinking about saving memory reading time by having cache memory inside our accelerator. Is that an option or we should just connect our accelerator to an onchip memory? We use SDRAM as our main memory.
Hi,
My apologies for not answering earlier. I didn't know of the existence of this mini-forum and did not receive any notifications for new posts!
How often do you expect to re-read the same things from the SDRAM? In particular, is what you are reading sequential in the SDRAM, or is it scattered? If the data is sequential and not too large, I think using a burst DMA transfer would not incur much overhead. If accesses are scattered though, a cache would certainly help (assuming you have a unique way to index elements).
If you do wish to use a cache though, you can certainly do so. You can use a single-port RAM for this. This element is available in the quartus library (on the right side of the main quartus window, NOT in qsys). You can find its docs here if you're interested:
https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_ram_rom.pdf
