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[Lab 2] Failure rate of my master unit scales with buffer size
Picture of Alexandre Chau
Alexandre Chau
Picture of Sahand Kashani-Akhavan
Sahand Kashani-Akhavan
 1
[Lab 3] Memory allocation
Picture of Alon Tchelet
Alon Tchelet
Picture of Sahand Kashani-Akhavan
Sahand Kashani-Akhavan
 5
Eclipse Crushes When Using 2 JTAGs
Picture of Alon Tchelet
Alon Tchelet
Picture of Alon Tchelet
Alon Tchelet
 0
Memory Write access with custom DMA to SDRAM
Picture of Amaury Pierre Jiezhi Wei
Amaury Pierre Jiezhi Wei
Picture of Amaury Pierre Jiezhi Wei
Amaury Pierre Jiezhi Wei
 9
[Lab 3] Multiple JTAG UART
Picture of Amaury Pierre Jiezhi Wei
Amaury Pierre Jiezhi Wei
Picture of Amaury Pierre Jiezhi Wei
Amaury Pierre Jiezhi Wei
 6
[LAB 3] Hardware Mailbox
Picture of Amaury Pierre Jiezhi Wei
Amaury Pierre Jiezhi Wei
Picture of René Beuchat
René Beuchat
 2
Custom instruction
Picture of Cédric Oliver Portmann
Cédric Oliver Portmann
Picture of Cédric Oliver Portmann
Cédric Oliver Portmann
 7
[Lab 3] top_level
Picture of Cédric Oliver Portmann
Cédric Oliver Portmann
Picture of Sahand Kashani-Akhavan
Sahand Kashani-Akhavan
 1
[LAB3] PIO not working
Picture of Cédric Oliver Portmann
Cédric Oliver Portmann
Picture of Matthias René Wüst
Matthias René Wüst
 2
[Lab2] Flash exceptions
Picture of Dominic Robert Heinrich Hagmann
Dominic Robert Heinrich Hagmann
Picture of Dominic Robert Heinrich Hagmann
Dominic Robert Heinrich Hagmann
 1
Register write/read problem
Picture of Jakub Lukasz Wieczorek
Jakub Lukasz Wieczorek
Picture of René Beuchat
René Beuchat
 1
Data Clarification
Picture of Jérôme Savary
Jérôme Savary
Picture of René Beuchat
René Beuchat
 2
Software profiling report_0.txt outputs only 0
Picture of Jérôme Savary
Jérôme Savary
Picture of Sahand Kashani-Akhavan
Sahand Kashani-Akhavan
 4
[Lab 3] RAM cells - not enough space
Picture of Jon Märki
Jon Märki
Picture of René Beuchat
René Beuchat
 1
[Lab 3] My code does nothing
Picture of Jon Märki
Jon Märki
Picture of Jon Märki
Jon Märki
 7
[Lab3] How much can we change the experiments?
Picture of Jon Märki
Jon Märki
Picture of René Beuchat
René Beuchat
 1
[LAB3] : JTAG DEBUG
Picture of Jonathan Magnin
Jonathan Magnin
Picture of Jonathan Magnin
Jonathan Magnin
 2
[LAB3] : Access Shared Ressources
Picture of Jonathan Magnin
Jonathan Magnin
Picture of Jonathan Magnin
Jonathan Magnin
 2
Clarification on Lab2 task
Picture of Leonardo Mussa
Leonardo Mussa
Picture of René Beuchat
René Beuchat
 2
DMA accelerator
Picture of Leonardo Mussa
Leonardo Mussa
Picture of Leonardo Mussa
Leonardo Mussa
 3
[Lab3] Clarification on questions
Picture of Leonardo Mussa
Leonardo Mussa
Picture of Sahand Kashani-Akhavan
Sahand Kashani-Akhavan
 4
[Lab 2] no gmon.out file and other issue
Picture of Loïc Karl Droz
Loïc Karl Droz
Picture of Loïc Karl Droz
Loïc Karl Droz
 2
[Lab 3] Set different CPU IDs for each subsystem
Picture of Loïc Karl Droz
Loïc Karl Droz
Picture of Loïc Karl Droz
Loïc Karl Droz
 0
Lab3 : Mailbox Issue
Picture of Luca Joss
Luca Joss
Picture of Luca Joss
Luca Joss
 7
Software Profiling
Picture of Lucas Biotto
Lucas Biotto
Picture of René Beuchat
René Beuchat
 1
Software Profiling, please HELP!
Picture of Lucas Biotto
Lucas Biotto
Picture of Sylvain Jean-Roger Migaud
Sylvain Jean-Roger Migaud
 13
Accelerator Master Interface Connection
Picture of Matthias René Wüst
Matthias René Wüst
Picture of Matthias René Wüst
Matthias René Wüst
 3
[Lab 3] Common access to LEDs
Picture of Matthias René Wüst
Matthias René Wüst
Picture of Sahand Kashani-Akhavan
Sahand Kashani-Akhavan
 1
[Lab 3] bss memory region
Picture of Philipp Thomas Nicolai Schuler
Philipp Thomas Nicolai Schuler
Picture of Philipp Thomas Nicolai Schuler
Philipp Thomas Nicolai Schuler
 7